1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, it relates to a nonvolatile semiconductor memory device which has a low-voltage (LV) transistor region and a high-voltage (HV) transistor region in a peripheral circuit section and which has a different element isolation structure in each of the regions.
2. Description of the Related Art
A NAND-type flash memory, for example, is a nonvolatile semiconductor memory device capable of electric rewriting (writing and erasing) of data. In this flash memory, a plurality of transistor circuits (peripheral circuit sections) are arranged around a memory cell section. The peripheral circuit sections of the flash memory are roughly classified into an LV transistor region and an HV transistor region.
Recently, element isolation regions have been increasingly miniaturized in the NAND-type flash memory. There has already been proposed a method of forming a silicon oxide film of, for example, non-doped silicate glass (NSG) by a coating method in the process of forming an embedded element isolation insulating film serving as shallow trench isolation (STI) (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2006-80942). That is, the coating method is used for the formation of the embedded element isolation insulating film in order to form a micro STI.
In particular, as compared with a polysilicon film, a polysilazane (PSZ) film formed by the coating method has good coverage characteristics and is therefore advantageous to the formation of the micro STI.
However, the PSZ film has the strong contraction stress. Thus, when the PSZ film is used for the STI of the peripheral circuit region, crystal defects tend to be happened in the LV transistor region, thus there is concern about problems such as junction leakage. This problem is dependent on the amount of the PSZ film and can be alleviated by reducing the amount of the film, that is, by reducing the depth of the STI. However, as the STIs in the LV and HV transistor regions of the peripheral circuit region are simultaneously formed, the reduction of the depth of the STI then leads to a problem such as an STI inversion leakage in the HV transistor region.
In addition, as a means of solving the above-mentioned problem, there has already been made a proposal that an STI is shaped to have a downward projection (see, for example, U.S. patent application U.S. Pat. No. 6,833,602).
As described above, a device having a shallow STI in an LV transistor region and a deep STI in an HV transistor region at the same time has been desired.